This invention relates to an FM stereo demodulator including circuit means for preventing audible clicking noises when the demodulator switches from a monaural to a stereo mode, and vice versa.
Conventional FM stereo demodulating circuits using a double balanced multiplier have a circuit construction such as that shown in FIG. 1, wherein a composite FM detector output is applied to an input terminal IN1. The FM detector output is also applied to a phase-locked-loop circuit 1 to derive a pilot signal and a sub-carrier to be used to perform the stereo mode demodulation in an in-phase relation to the FM detector output, i.e., the composite signal and the sub-carrier are applied to input terminals IN2 and IN4, respectively, of a double balanced multiplier 3. The pilot signal of 19KHz derived from the phase locked loop circuit 1 is used to obtain a 19KHz signal in-phase with the pilot signal contained in the composite signal by a phase detector 2. That is, the phase detector 2 provides an output of 19KHz whose level is in proportion to the level of the pilot signal contained in the composite signal. The output of the phase detector 2 is applied to one of the input terminals of an AND circuit 5, the other input IN3 being supplied with a stereo control signal to be described later. The AND circuit 5, which may have any conventional construction, provides an output when the output of the phase detector 2 is at or higher than a certain level and the stereo control signal is applied to the other input IN3.
FIG. 4c shows an inverted IF output versus an antenna input frequency. This may be used as the stereo control signal to be applied to the terminal IN3 of the AND circuit 5. In order to obtain a sharp edge, the waveform in FIG. 4c is appropriately shaped to obtain a waveform as shown in FIG. 4b.
The output of a composite signal detector (not shown) takes the form of an S shaped, substantial d.c. voltage or current superposed by high frequency components as shown in FIG. 4a. Since the S curve covers a range wider than 2.DELTA.f', the width 2.DELTA.f of the control signal falls within the range 2.DELTA.f'. Therefore, the pilot signal can be detected prior to the stereo control signal.
The output of the phase detector 2, which is a signal of 19KHz in phase with the pilot signal contained in the composite signal, is first applied to the one input of the AND circuit 5 when the tuning frequency approaches the IF frequency f.sub.o. When the tuning frequency reaches one edge of the stereo control signal in FIG. 4b, it is applied to the terminal IN3 of the AND circuit 5 to supply the signal of 19KHz to one input of a bias switch circuit 4 whose other input is connected to the output of the phase locked loop 1 to receive the subcarrier of 38 KHz.
FIG. 3a shows an example of the construction of the bias switch circuit 4. The output of the AND circuit 5 is applied to a base of a transistor Q through a diode D to bias the transistor to conduct. The signal of 38KHz from the phase locked loop 1 is also applied to the base, so that the latter is amplified. When the transistor Q conducts, a relay coil L is actuated to close a lamp circuit PL to indicate the stereo mode.
The output of the bias switch circuit 4 is applied to an input terminal IN4 of the double balanced multiplier 3.
FIG. 3b shows a typical circuit construction of the double balanced multiplier 3. In FIG. 3b, a first pair of common emitter transistors Q1 and Q2 and a second pair of common emitter transistors Q3 and Q4 form switching circuits. Each of the switching circuits performs a switching operation in response to the application of the subcarrier signal to input IN4. Transistors Q5 and Q6 form a differential amplifier. Transistors Q3, Q4 and Q6 further form a crosstalk and subcarrier cancelling circuit. The base input IN2 of transistor Q5 is supplied with the composite signal, and the base of transistor Q6 is supplied with a fixed biasing voltage. From a collector terminal OUT1, to which the collectors of transistors Q2 and Q4 are connected, a right channel output is derived through a load resistor R2, and from a collector terminal OUT2, to which the collectors of transistors Q1 and Q3 are connected, a left channel output is derived through a load resistor R1.
In the conventional circuit construction described above, when the tuning frequency approaches a stereophonic broadcast, the double balanced multiplier 3 is switched from the monaural mode to the stereo mode at the time when the tuning frequency reaches the edge of the range 2.DELTA.f in FIG. 4b. At that time a distinct clicking noise is often produced in the output terminals OUT1 and OUT2 of the double balanced multiplier 3 due to characteristic unbalances of the circuit elements, such as transistors, etc., constituting the multiplier.
That is, when the circuit of FIG. 3b is operating in the monaural mode a positive in-phase biasing voltage is supplied across terminal IN4, so that the transistors Q1-Q4 are in an on state to provide the same outputs at terminals OUT1 and OUT2. Representing the collector currents of transistors Q5 and Q6 as I.sub.1 and I.sub.2, respectively, the collector currents of transistors Q1-Q4 as kI.sub.1, (1-k)I.sub.1, k'I.sub.2 and (1-k')I.sub.2, respectively, and the currents of the load resistors R1 and R2 as I.sub.L and I.sub.R, respectively, then the load currents I.sub.L and I.sub.R may be defined as follows for the monaural mode: EQU I.sub.L = kI.sub.1 + k'I.sub.2 ( 1) EQU i.sub.r = (1-k)I.sub.1 + (1-k')I.sub.2 ( 2).
in the stereo mode, on the other hand, the average load currents are as follows: EQU I.sub.L = 1/2(I.sub.1 + I.sub.2) (3) EQU i.sub.r = 1/2(i.sub.1 + i.sub.2) (4).
if there is any difference between equations (1) and (3) and between equations (2) and (4), then a clicking noise will be produced when the operation mode is switched between monaural and stereo, i.e., at the transient time of switching.
Assuming that: EQU .vertline.equation (3) - equation (1).vertline. = I.sub.PL, and (5) EQU .vertline.equation (4) - equation (2).vertline. = I.sub.PR, (6)
then it follows that, by substitution: EQU I.sub.PL = .vertline.1/2(I.sub.1 +I.sub.2)-(kI.sub.1 +k'I.sub.2).vertline.= .vertline.1/2{(1-2k)I.sub.1 +(1-2k')I.sub.2 }.vertline. (7) EQU i.sub.pr = .vertline.1/2(i.sub.1 +i.sub.2)-{(1-k)I.sub.1 +(1-k')I.sub.2 }.vertline. = .vertline.1/2{(2k1)I.sub.1 +(2k'-1)I.sub.2 }.vertline.(8)
in equations (7) and (8), if the collector current of transistor Q1 is equal to that of transistor Q2, and if the collector current of transistor Q3 is equal to that of transistor Q4, then the constants k and k' are both equal to 0.5 and I.sub.PL =I.sub.PR =0. In this case, there is no possibility of any clicking noise in the terminals OUT1 and OUT2 even when the mode is suddenly switched from monaural to stereo. However, as a practical matter the constants k and k' may not always equal 0.5 due to characteristic unbalances of the paired circuit elements in the multiplier 3. As a result, I.sub.PL and I.sub.PR may not be zero in the monoaural mode. Since in the stereo mode I.sub.PL and I.sub.PR are always necessarily equal to each other, any difference between I.sub.PL and I.sub.PR in the monaural mode must be reduced immediately upon switching. The clicking noise is produced as a result of such transient changes of I.sub.PL and I.sub.PR.